Group-III nitride semiconductors, GaN and AlGaN in particular, have a high breakdown voltage due to their wide band gap. GaN and AlGaN facilitate formation of a hetero structure, such as AlGaN/GaN. In a hetero structure such as AlGaN/GaN, a channel with higher concentrations of electrons (two-dimensional electron gas layer, 2DEG layer) is generated on the GaN layer side at the AlGaN/GaN interface, by piezoelectricity caused due to lattice constant difference between AlGaN and GaN and by their band gap difference. This allows large current and high speed operations. In view of this, group-III nitride semiconductors are expected to be applied to electronic devices, such as a power field effect transistor (FET) or a diode.
Due to the large current operation, for example, a hetero-FET (HFET, not illustrated), with a general planar AlGaN/GaN structure having an Al composition of 25% and a thickness of 20 nm, is normally on with a negative threshold voltage. In the light of safety, however, there is a strong demand for a general circuit which includes a power FET to be normally off with a positive threshold voltage.
FIG. 1 illustrates an example of a cross-sectional structure of a general normally-off AlGaN/GaN-HFET disclosed in Patent Literature (PTL) 1. The AlGaN/GaN-HFET illustrated in FIG. 1 is formed as described below.
First, a group-III nitride semiconductor (for example, GaN) serving as a channel layer 1 is formed on, for example, a given substrate (such as a substrate of Sic, Sapphire, Si or GaN, not illustrated), or a buffer layer (a buffer layer comprising a combination of different group-III nitride semiconductors, in particular AlN, AlGaN, GaN and the like, not illustrated). Subsequently, a carrier supply layer 2 (for example, AlGaN) is formed which has a band gap larger than that of the channel layer 1, and a 2DEG layer 3 is generated on the channel layer side at the interface between the channel layer 1 and the carrier supply layer 2.
Subsequently, a capping layer 4 comprising a p-type group-III nitride semiconductor (for example, p-AlGaN) is selectively formed, and a source electrode 5a and a drain electrode 5b which form ohmic contacts are sequentially formed. A gate electrode 6 which forms an ohmic contact or Schottky contact is formed on the p-type capping layer 4 located between the source electrode 5a and the drain electrode 5b. Here, the source electrode 5a and the drain electrode 5b may be arranged at any position as long as the source electrode 5a and the drain electrode 5b are separately located on either side of the p-type capping layer 4. The ohmic electrodes may contact, for example, the group-III nitride semiconductor carrier supply layer 2 or the group-III nitride semiconductor channel layer 1 (that is, an ohmic recess structure may be provided).
The carrier supply layer 2 of group-III nitride semiconductor is generally of n-type. Hence, a natural depletion layer is formed between the p-type capping layer 4 and the carrier supply layer 2, and thus, a depletion region is created in a state where no voltage is applied to the gate electrode 6. Hence, the carrier supply layer 2 below the gate can be thick in order to achieve normally-off operation. In order to facilitate understanding, FIG. 1 illustrates a state where the gate electrode 6 is positively biased and the 2DEG layer 3 is generated below the gate.
Each of the source electrode 5a and the drain electrode 5b comprises an electrode including one metal or two or more metals selected from among Ti, Al, Mo, Hf, and the like. The gate electrode 6 comprises an electrode including one metal or two or more metals selected from among Ti, Al, Ni, Pt, Pd, Au, and the like.
Furthermore, for a power device, reduction in on-resistance (Ron) of a FET is important as well as normally-off operation.
Ron is a resistance value obtained from the slope of current rise of Ids-Vds characteristics of a device. It is ideal for a power device to have Ron that is as low as possible within a desired withstand voltage range. Ron is approximately equal to a sum of source resistance (Rs: source-gate resistance), drain resistance (Rd: gate-drain resistance), and channel resistance below the gate (Rch: resistance of the channel immediately below the gate). Strictly speaking, Ron also includes interconnection resistance, but it is omitted here. Accordingly, it is necessary to reduce Rs, Rd, and Rch to reduce Ron.
Rch depends on the gate length or sheet resistance of an epitaxial substrate; and thus, there is a limit on reduction in Rch. Rd is mainly defined by the contact resistance (Rc) of the drain electrode and the sheet resistance of an epitaxial substrate between the gate and drain electrodes. In order to ensure withstand voltage of a high-voltage power device, however, a certain level of gate to drain distance (Lgd) is necessary. Hence, reduction in Rc is important to reduce Rd. Rs is mainly defined by the contact resistance (Rc) of the source electrode and the sheet resistance of an epitaxial substrate between the source and gate electrodes. Rs is not related to withstand voltage, and thus, it is better to reduce Rs as much as possible to improve Ron.
Although the sheet resistance of the epitaxial substrate between the source and gate electrodes significantly depends on the source-to-gate distance, the source-to-gate distance is defined to a given minimum distance in the light of process margin. Hence, there is a limit on reduction in the sheet resistance of the epitaxial substrate between the source and gate electrodes.
In conclusion, reduction in Rc and in sheet resistance of the epitaxial substrate between the source and gate electrodes are important to reduce Ron. In particular, since Rc exists both on the source electrode side and the drain electrode side, reduction in Rc has a double effect. Hence, reduction in Rc is the most important to reduce Ron.
FIG. 2 illustrates an example of a cross-sectional structure of a general AlGaN/GaN-HFET with a reduced contact resistance disclosed in PTL 2. The AlGaN/GaN-HFET illustrated in FIG. 2 is formed as described below.
First, a group-III nitride semiconductor (for example, GaN) serving as a channel layer 8 is formed on, for example, a given substrate (such as a substrate of Sic, Sapphire, Si or GaN, not illustrated), or a buffer layer (a buffer layer comprising a combination of different group-III nitride semiconductors, in particular, AlN, AlGaN, GaN and the like, not illustrated). Subsequently, a carrier supply layer 9 (for example, AlGaN) is formed which has a band gap larger than that of the channel layer 8, and a 2DEG layer 10 is generated on the channel layer side at the interface between the channel layer 8 and the carrier supply layer 9.
Subsequently, a capping layer 11 comprising a group-III nitride semiconductor doped with n-type dopant such as Si (for example, n-GaN) is formed, and a second capping layer 12 comprising a group-III nitride semiconductor (for example, AlGaN) is further formed. The surface of the stack of the group-III nitride semiconductors is etched by a known dry etching technique to form a recessed portion 13.
Subsequently, a source electrode 14a and a drain electrode 14b which form ohmic contacts are formed on the second capping layer 12 other than the recessed portion, and a gate electrode 15 which forms a Schottky contact is formed in the recessed portion 13. Each of the source electrode 14a and the drain electrode 14b comprises an electrode including one metal or two or more metals selected from among Ti, Al, Mo, Hf, and the like. The gate electrode 15 comprises an electrode including one metal or two or more metals selected from among Ni, Pt, Pd, Au, and the like.
FIG. 3 illustrates an example of a cross-sectional structure of an AlGaN/GaN-HFET in which a method of reducing contact resistance is applied to group-III nitride semiconductors. The method uses an n+ doped capping layer and is widely used for GaAs, too. The AlGaN/GaN-HFET illustrated in FIG. 3 is formed as described below.
First, a group-III nitride semiconductor (for example, GaN) serving as a channel layer 16 is formed on, for example, a given substrate (such as a substrate of Sic, Sapphire, Si or GaN, not illustrated), or a buffer layer (a buffer layer comprising a combination of different group-III nitride semiconductors, in particular, AlN, AlGaN, GaN and the like, not illustrated). Subsequently, a carrier supply layer 17 (for example, AlGaN) which has a band gap larger than that of the channel layer 16 is formed, and a 2DEG layer 18 is generated on the channel layer side at the interface between the channel layer 16 and the carrier supply layer 17.
Then, an n-type capping layer 19 is formed which comprises a group-III nitride semiconductor heavily doped with n-type dopant, such as Si, (for example, n+-GaN). The surface of the stack of the group-III nitride semiconductors is etched by a known dry etching technique (or selectively etched) to form a recessed portion 20.
Subsequently, a source electrode 21a and a drain electrode 21b which form ohmic contacts are formed on the n-type capping layer 19 other than the recessed portion, and a gate electrode 22 which forms a Schottky contact is formed in the recessed portion 20. Each of the source electrode 21a and the drain electrode 21b comprises an electrode including one metal or two or more metals selected from among Ti, Al, Mo, Hf, and the like. The gate electrode 22 comprises an electrode including one metal or two or more metals selected from among Ni, Pt, Pd, Au, and the like.